The present invention generally relates to integrated circuit (IC) memory devices and, more particularly, to a process for protecting thin gate oxides by covering polysilicon studs during gate oxidation in vertical metal oxide semiconductor field effect transistor (MOSFET) dynamic random access memory (DRAM) arrays.
A DRAM circuit usually includes an array of memory cells interconnected by rows and columns, which are known as wordlines (WLs) and bitlines (BLs), respectively. Typically, a DRAM memory cell comprises a MOSFET connected to a capacitor, such as a vertical MOSFET having a trench capacitor. Vertical MOSFETs allow for an effective size reduction in bit densities, and as such, the use of such vertical MOSFETs has increased over the years as the need to overcome the scalability limitations of planar MOSFET DRAM access transistors has also increased.
The use of vertical MOSFETs is not yet widespread and several characteristics need to be optimized. In particular, in the formation of a memory cell in vertical MOSFET DRAM arrays, an array top oxide (ATO) is needed to isolate the passing word-lines from active areas on the substrate. Typical processes for forming these isolating ATO areas include forming an array top oxide layer in the presence of a pad nitride layer of the DRAM. A variety of methods exist in the art for forming array top oxides, such as, top oxide early, top oxide nitride and top oxide late procedures.
Typically, in a top oxide early (TOE) procedure, an array top oxide area is formed with pad nitride being present in the support. Any remaining pad nitride in the support is then removed, a gate oxide is grown and then a gate poly is deposited. Similarly, in top oxide nitride (TON) procedures, an array top oxide area is formed after the pad nitride has been stripped in both the array and support areas. Array top oxide is then removed in the support followed by gate oxidation and deposition of a gate poly. However, a disadvantage of such procedures is that both TOE and TON processing require a large number of masks, and thus processing steps, for fabrication of these ATO areas.
Further procedures for forming array top oxide areas include a top oxide late (TOL) scheme. In TOL processing, a pad nitride layer is removed from the entire surface of the DRAM. Thereafter, a gate oxide is grown and a gate poly is deposited in the support area. An array top oxide layer is then deposited after removal of the gate poly in the array. The advantages of TOL processing include reduced number of masks, processing steps and manufacturing costs as well as providing a litho-friendly structure with a flat surface after the top oxide CMP in comparison to TOE and TON processes. However, it is significantly more difficult to achieve compared to TOE and TON.
Additionally, during TOL fabrication of the gate oxidation for support devices in vertically-arranged-device memory cells arsenic from the gate poly of the vertical array devices, i.e., polysilicon stud, can out-diffuse and react with the nitrogen. This undesirably results in thicker oxides in the thin gate oxide regions, which in turn, increases the Vt of the support device. Numerous steps are required, including depositing a liner layer over the polysilicon stud, in order to prevent the out-diffusion of arsenic during the formation of the gate oxidation for support devices in vertical DRAM.
Accordingly, a need continues to exist in the art for providing further improved, simplified techniques of forming an array top oxide area in vertical DRAM that require a reduced number of masks, processing steps and manufacturing costs, provides a litho-friendly structure, and prevents out-diffusion of arsenic from the gate poly during TOL fabrication of the gate oxidation for the support devices in the vertical memory cell.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved and simplified method for forming an array top oxide area in vertical DRAM.
Another object of the present invention is to provide a method for forming an array top oxide area in vertical DRAM via an improved, simplified top oxide late (TOL) scheme that protects thin gate oxides during gate oxidation by covering the polysilicon studs of the vertical DRAM.
It is another object of the present invention to provide a method for forming an array top oxide area in vertical DRAM that requires a reduced number of masks and processing steps.
A further object of the invention is to provide a method for forming an array top oxide area in vertical DRAM that prevents out-diffusion of arsenic from the gate poly during TOL fabrication of the gate oxidation for the support devices in the vertical memory cell.
It is yet another object of the present invention to provide a method for forming an array top oxide area in vertical DRAM that reduces costs.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention, which, is directed to in a first aspect a method of providing an array top oxide over an array of trenches containing trench capacitors and overlying vertical transistors. The method includes providing a substrate having a first area and a second area. Preferably, the first area is an array area, while the second area is a support area. A sacrificial oxide layer is provided over the first and second areas and such sacrificial oxide layer is removed only from the second area. A gate oxide layer is then provided over the second area and a gate conductor layer deposited over both first and second areas. The gate conductor layer is then removed only from the first area. Subsequently, an array top oxide layer is deposited over the first and second areas, and the array top oxide layer is removed from the second area so as to leave remaining portions of the array top oxide layer only in the first area.
Prior to the step of growing the sacrificial oxide layer, the method may further include removing a pad nitride layer in both the first and second areas to expose a pad oxide layer in both the first and second areas, removing at least a portion of the pad oxide layer from both the first and second areas and then growing the sacrificial oxide layer over exposed surface areas of the substrate. The first and second areas may then be implanted.
The sacrificial oxide layer may be removed from the second area only by providing a mask over the first area to protect the first area during the sacrificial oxide layer removal processing. This mask is removed from second area prior to growing the gate oxide.
Gate oxide is grown at least in the second area, and gate conductor is deposited in the first and the second area.
Further, the gate conductor layer may be removed from the first area also by providing a mask over the second area to protect the second area during the gate conductor layer removal processing. This mask is removed prior to depositing the array top oxide layer.
In another aspect, the invention relates to a method of providing an array top oxide over an array of trenches containing trench capacitors and overlying vertical transistors. The method includes providing a substrate having an array area and a support area and then providing a sacrificial oxide layer over the array and support areas. The sacrificial oxide layer is removed from the support area and then a gate oxide layer is provided over the support area. A gate conductor layer is then deposited over the array and support areas and the gate conductor layer removed from the array area only. An array top oxide layer is then deposited over the array and support areas. This array top oxide layer may be deposited by high density plasma deposition. The array top oxide layer is removed from the support area by planarization so as to leave remaining portions of the array top oxide layer only in the array area. In removing the sacrificial oxide layer only from the support area, a first mask is provided over the array area to protect such array area during the sacrificial oxide layer removal processing. This first mask is then removed from the array area prior to providing the gate oxide layer over the support area. A second mask is then provided over the support area to protect the support area during the gate conductor layer removal processing. The second mask is also removed prior to depositing the array top oxide layer. These first and second masks may both comprise etch support lithography masks.
In accordance with the invention, the step of removing the sacrificial oxide layer only from the support area prevents out-diffusion from the array area, particularly arsenic out-diffusion, while during the step of growing the gate oxide layer over the support area, the sacrificial oxide layer protects the underlying array area to also prevent any out-diffusion there-from, particularly arsenic out-diffusion.